Some network printers in which a printer and a host computer are connected through a network are configured so that the main body of the printer does not have a function that expands image data and the host side performs image compression after performing expansion processing together with image processing. In this configuration, the printer apparatus receives the compressed image data and stores it on an internal memory. Upon commencement of a printing operation, the printer apparatus decompresses the compressed image data that was stored on the internal memory by use of a decompression circuit while transferring the data to a recording unit (engine unit) to conduct printing.
Basically, in most cases the maximum printing speed of a printer is calculated taking ordinary image data as a standard. Accordingly, when printing image data that is different to the standard, there are cases in which the speed decreases. That is, in this type of printer apparatus the decompression speed of the decompression circuit can become a bottleneck with respect to speeding up the print operation. In order to realize the maximum speed for a print operation, it is desirable to make the processing speed of the decompression circuit faster than the speed of supplying image data to the engine unit. For example, in the compression/decompression methods that are normally used, in some cases time is required for decompression depending on which compression code is used. Therefore, to ensure that the decompression speed does not become slower than the printing speed (speed of supplying image data to an engine unit), some kind of specific configuration is also required for cases in which such types of compression codes that increase the decompression time occur in succession.
The processing speed of a decompression circuit is basically dependent on the operation clock of the decompression circuit. Therefore, in order not to cause a reduction in the speed of a print operation, in cases in which the above described types of compression codes for which time is required for decompression occur in succession, it is sufficient that the operation clock of the decompression circuit be set so that the decompression speed is faster than the speed of supplying image data to the engine unit.
However, the probability of the successive occurrence of the above described types of compression codes which require time for decompression is itself low. Thus, it is wasteful to set the operation clock at a high speed only for the purpose of ensuring the decompression speed in cases where these types of compression codes for which the probability of occurrence is low are input. More specifically, when an apparatus is configured to apply a high speed operation clock to prepare for a case where a compression code which requires time for decompression occurs in succession, it can be considered that the operation clock is unnecessarily fast in most cases in which such type of compression code does not occur in succession. Thus, not only is power wastefully consumed, but the heat generation of the apparatus itself or the IC is also increased. This also results in shortening the lifetime of the device or increasing the failure rate.
In this regard, Japanese Patent Laid-Open No. 2001-027986 discloses, for example, technology equipped with a software codec (compressor/decompressor) and a hardware codec that is used to select an advantageous method for high-speed processing. This technology enables the speeding up of processing.
However, the technology disclosed in the aforementioned Japanese Patent Laid-Open No. 2001-027986 results in an increase in circuit size, and by extension an increase in power consumption. Meanwhile, Japanese Patent Laid-Open No. 2001-184495 discloses an image processing apparatus having a plurality of programmable image processing means of different architecture for performing image processing. The aforementioned Japanese Patent Laid-Open No. 2001-184495 discloses technology that reduces power consumption by stopping the clock supply to image processing means that are not used among the plurality of image processing means.
In a case in which the decompression speed of a decompression circuit has become a bottleneck with respect to accelerating a print operation, to avoid causing a reduction in the speed of the print operation, instead of speeding up the operation clock of the decompression circuit as described above, it is also possible to adopt a configuration in which a buffer memory is provided for storing decompressed image data at a stage that is subsequent to the decompression circuit. More specifically, the decompression operation is started at a timing that is earlier than the start of the print operation to thereby store the decompressed image data in the buffer in advance. As a result, it is possible to absorb a difference between the decompression speed of the decompression circuit and the speed of supplying image data to the engine unit. Since this configuration can be implemented without accelerating the operation clock of the decompression circuit, it is advantageous from the viewpoint of power consumption.
However, when adopting this type of configuration, conventionally, since a difference between the decompression speed of the decompression circuit and the speed of supplying image data to the engine unit is large, it is necessary to provide a large storage capacity for the buffer memory. Consequently, there is a problem that this kind of configuration entails an increase in cost. Further, with regard to cost increases, this is also a serious problem for the aforementioned Japanese Patent Laid-Open No. 2001-027986 and Japanese Patent Laid-Open No. 2001-184495 that are provided with a plurality of codecs or image processing means having a cost that is higher than the memory.
Thus, in realizing a speeding up of printing operations it is difficult to achieve compatibility between both low cost and low power consumption according to any of the above methods (especially, according to either the aforementioned Japanese Patent Laid-Open No. 2001-027986 or Japanese Patent Laid-Open No. 2001-184495).